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# Created by write_sdc
# Wed Jul 31 04:11:43 2024
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current_design mor1kx
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# Timing Constraints
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create_clock -name clk -period 1.0000 [get_ports {clk}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_addr_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_stall_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_stb_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_we_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_ack_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_err_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_rty_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {irq_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_ack_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_err_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_rty_i}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_coreid_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {multicore_numcores_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {rst}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[16]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[17]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[18]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[19]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[20]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[21]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[22]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[23]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[24]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[25]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[26]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[27]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[28]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[29]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[30]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[31]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_adr_i[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {snoop_en_i}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_ack_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_dat_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {du_stall_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_adr_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_bte_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_bte_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_cti_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_cti_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_cti_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_cyc_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_dat_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_sel_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_sel_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_sel_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_sel_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_stb_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {dwbm_we_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_adr_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_bte_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_bte_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_cti_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_cti_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_cti_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_cyc_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_dat_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_sel_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_sel_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_sel_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_sel_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_stb_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {iwbm_we_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_insn_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jal_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jb_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jbtarget_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_jr_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_pc_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_valid_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[16]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[17]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[18]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[19]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[20]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[21]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[22]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[23]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[24]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[25]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[26]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[27]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[28]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[29]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[30]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[31]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbdata_o[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wben_o}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbreg_o[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbreg_o[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbreg_o[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbreg_o[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {traceport_exec_wbreg_o[4]}]
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# Environment
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# Design Rules
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